CY8C24094, CY8C24794
CY8C24894, CY8C24994
®
PSoC Programmable System-on-Chip™
■ Full Speed USB (12 Mbps)
❐ Four Uni-Directional Endpoints
❐ One Bi-Directional Control Endpoint
❐ USB 2.0 Compliant
1. Features
■ XRES Pin to Support In-System Serial Programming (ISSP)
and External Reset Control in CY8C24894
❐ Dedicated 256 Byte Buffer
❐ No External Crystal Required
■ Powerful Harvard Architecture Processor
❐ M8C Processor Speeds to 24 MHz
❐ Two 8x8 Multiply, 32-Bit Accumulate
❐ Low Power at High Speed
❐ 3V to 5.25V Operating Voltage
❐ Industrial Temperature Range: -40°C to +85°C
❐ USB Temperature Range: -10°C to +85°C
■ Flexible On-Chip Memory
❐ 16K Flash Program Storage 50,000 Erase and Write Cycles
❐ 1K SRAM Data Storage
❐ In-System Serial Programming (ISSP)
❐ Partial Flash Updates
❐ Flexible Protection Modes
®
■ Advanced Peripherals (PSoC Blocks)
❐ EEPROM Emulation in Flash
❐ 6 Rail-to-Rail Analog PSoC Blocks Provide:
• Up to 14-Bit ADCs
■ Programmable Pin Configurations
• Up to 9-Bit DACs
❐ 25 mA Sink, 10 mA Drive on all GPI/O
• Programmable Gain Amplifiers
• Programmable Filters and Comparators
❐ 4 Digital PSoC Blocks Provide:
• 8 to 32-Bit Timers, Counters, and PWMs
• CRC and PRS Modules
❐ Pull Up, Pull Down, High Z, Strong, or Open Drain Drive
Modes on all GPI/O
❐ Up to 48 Analog Inputs on GPI/O
❐ Two 33 mA Analog Outputs on GPI/O
❐ Configurable Interrupt on all GPI/O
■ Precision, Programmable Clocking
• Full-Duplex UART
❐ Internal ±4% 24 and 48 MHz Oscillator
❐ Internal Oscillator for Watchdog and Sleep
❐ 0.25% Accuracy for USB with no External Components
• Multiple SPI™ Masters or Slaves
• Connectable to all GPI/O Pins
❐ Complex Peripherals by Combining Blocks
❐ Capacitive Sensing Application Capability
■ Additional System Resources
2
❐ I C Slave, Master, and Multi-Master to 400 kHz
❐ Watchdog and Sleep Timers
❐ User Configurable Low Voltage Detection
A n a lo g
P o r t
5
P o r t
4
P o r t
3
P o r t
2
P o r t
1
P o r t
0
P o r t
7
D
r iv e r s
2. Logic Block Diagram
G lo b a l D ig ita l In te r c o n n e c t
G lo b a l A n a lo g In te r c o n n e c t
P S o C C O R E
S R A M
1 K
S R O M
F la s h 1 6 K
S le e p a n d
a tc h d o g
C P U C o r e ( M 8 C )
W
In te r r u p t
C o n tr o lle r
C lo c k S o u r c e s
( In c lu d e s I M O a n d IL O )
D IG IT A L S Y S T E M
A N A L O G S Y S T E M
A n a lo g
R e f.
D i g i t a l
B lo c k
A r r a y
A n a lo g
B l o c k
A r r a y
In te r n a l
V o lta g e
R e f.
A n a lo g
In p u t
D ig ita l
C lo c k s
2
D e c im a to r
T y p e
P O R a n d L V D
S y s te m R e s e ts
I 2 C
U S B
M
A C s
2
M
u x in g
S Y S T E M R E S O U R C E S
Cypress Semiconductor Corporation
Document Number: 38-12018 Rev. *M
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised February 10, 2009
CY8C24094, CY8C24794
CY8C24894, CY8C24994
Figure 3-2. Analog System Block Diagram
3.1 The Analog System
A ll IO
(E x c e p t P o rt 7 )
The Analog System is composed of 6 configurable blocks, each
comprised of an opamp circuit allowing the creation of complex
analog signal flows. Analog peripherals are very flexible and can
be customized to support specific application requirements.
Some of the more common PSoC analog functions (most
available as user modules) are listed below.
P 0 [7 ]
P 0 [5 ]
P 0 [6 ]
P 0 [4 ]
P 0 [3 ]
P 0 [1 ]
P 0 [2 ]
P 0 [0 ]
■ Analog-to-digital converters (up to 2, with 6 to 14-bit resolution,
selectable as Incremental, Delta Sigma, and SAR)
P 2 [6 ]
P 2 [4 ]
P 2 [3 ]
P 2 [1 ]
■ Filters (2 and 4 pole band-pass, low-pass, and notch)
■ Amplifiers (up to 2, with selectable gain to 48x)
■ Instrumentation amplifiers (1 with selectable gain to 93x)
■ Comparators (up to 2, with 16 selectable thresholds)
■ DACs (up to 2, with 6- to 9-bit resolution)
P 2 [2 ]
P 2 [0 ]
■ Multiplying DACs (up to 2, with 6- to 9-bit resolution)
A C I0 [1 :0 ]
A rra y In p u t
A C I1 [1 :0 ]
■ High current output drivers (two with 30 mA drive as a PSoC
Core Resource)
C o n fig u ra tio n
■ 1.3V reference (as a System Resource)
■ DTMF Dialer
B lo c k
A rray
A C B 0 0
A S C 1 0
A S D 2 0
A C B 0 1
■ Modulators
A S D 1 1
A S C 2 1
■ Correlators
■ Peak Detectors
A n a lo g R e fe re n c e
■ Many other topologies possible
In te rfa c e to
D ig ita l S y s te m
R e fe re n c e
G e n e ra to rs
Analog blocks are arranged in a column of three, which includes
one CT (Continuous Time) and two SC (Switched Capacitor)
blocks, as shown in Figure 3-2.
R e fH i
R e fL o
A G N D
A G N D In
R e fIn
B a n d g a p
M 8 C In te rfa c e (A d d re s s B u s , D a ta B u s , E tc .)
3.0.1 The Analog Multiplexer System
The Analog Mux Bus can connect to every GPI/O pin in ports 0-5.
Pins are connected to the bus individually or in any combination.
The bus also connects to the analog system for analysis with
comparators and analog-to-digital converters. It is split into two
sections for simultaneous dual-channel processing. An
additional 8:1 analog input multiplexer provides a second path to
bring Port 0 pins to the analog array.
Switch control logic enables selected pins to precharge continu-
ously under hardware control. This enables capacitive
measurement for applications such as touch sensing. Other
multiplexer applications include:
■ Track pad, finger sensing.
■ Chip-wide mux that allows analog input from up to 48 I/O pins.
■ Crosspoint connection between any I/O pin combinations.
When designing capacitive sensing applications, refer to the
Resources > Application Notes. In general, and unless otherwise
noted in the relevant Application Notes, the minimum
signal-to-noise ratio (SNR) for CapSense applications is 5:1.
Document Number: 38-12018 Rev. *M
Page 3 of 47
CY8C24094, CY8C24794
CY8C24894, CY8C24994
3.1 Additional System Resources
4. Getting Started
System Resources, provide additional capability useful to
complete systems. Additional resources include a multiplier,
decimator, low voltage detection, and power on reset. Brief state-
ments describing the merits of each resource follow.
The quickest way to understand PSoC silicon is to read this data
sheet and then use the PSoC Designer Integrated Development
Environment (IDE). This data sheet is an overview of the PSoC
integrated circuit and presents specific pin, register, and
electrical specifications.
■ Full-Speed USB (12 Mbps) with 5 configurable endpoints and
256 bytes of RAM. No external components required except
two series resistors. Wider than commercial temperature USB
operation (-10°C to +85°C).
For in depth information, along with detailed programming
details, see the PSoC® Programmable System-on-Chip
Technical Reference Manual for CY8C28xxx PSoC devices.
■ Digital clock dividers provide three customizable clock
frequencies for use in applications. The clocks can be routed
to both the digital and analog systems. Additional clocks are
generated using digital PSoC blocks as clock dividers.
For up-to-date ordering, packaging, and electrical specification
4.1 Application Notes
■ Two multiply accumulates (MACs) provide fast 8-bit multipliers
with 32-bit accumulate, to assist in both general math and
digital filters.
Application notes are an excellent introduction to the wide variety
www.cypress.com/psoc. Select Application Notes under the
Documentation tab.
■ Decimator provides a custom hardware filter for digital signal
processing applications including creation of Delta Sigma
ADCs.
4.2 Development Kits
■ TheI2Cmoduleprovides100and400kHzcommunicationover
two wires. Slave, master, multi-master are supported.
www.cypress.com/shop and through a growing number of
regional and global distributors, which include Arrow, Avnet,
Digi-Key, Farnell, Future Electronics, and Newark.
■ Low Voltage Detection (LVD) interrupts signal the application
of falling voltage levels, while the advanced POR (Power On
Reset) circuit eliminates the need for a system supervisor.
4.3 Training
■ An internal 1.3V reference provides an absolute reference for
the analog system, including ADCs and DACs.
training covers a wide variety of topics and skill levels to assist
you in your designs.
■ Versatile analog multiplexer system.
3.2 PSoC Device Characteristics
4.4 CyPros Consultants
Depending on your PSoC device characteristics, the digital and
analog systems can have 16, 8, or 4 digital blocks and 12, 6, or
4 analog blocks. The following table lists the resources available
for specific PSoC device groups. The device covered by this data
sheet is shown in the highlighted row of the table
Certified PSoC Consultants offer everything from technical
4.5 Solutions Library
www.cypress.com/solutions. Here you can find various appli-
cation designs that include firmware and hardware design files
that enable you to complete your designs quickly.
Table 3-1. PSoC Device Characteristics
PSoC Part
Number
4.6 Technical Support
CY8C29x66
CY8C27x43
up to
64
4
2
16
8
12
12
4
4
4
4
12
12
2K
32K
16K
find an answer to your question, call technical support at
1-800-541-4736.
up to
44
256
Bytes
CY8C24x94
56
1
1
4
4
48
12
2
2
2
2
6
6
1K
16K
4K
CY8C24x23A
up to
24
256
Bytes
[1]
CY8C21x34
CY8C21x23
CY8C20x34
up to
28
1
1
0
4
4
0
28
8
0
0
0
2
2
0
4
4
3
512
8K
4K
8K
Bytes
[1]
[2]
16
256
Bytes
up to
28
28
512
Bytes
Document Number: 38-12018 Rev. *M
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CY8C24094, CY8C24794
CY8C24894, CY8C24994
5.1.4 Code Generation Tools
5. Development Tools
PSoC Designer supports multiple third party C compilers and
assemblers. The code generation tools work seamlessly within
the PSoC Designer interface and have been tested with a full
range of debugging tools. The choice is yours.
PSoC Designer is a Microsoft® Windows-based, integrated
development
environment
for
the
Programmable
System-on-Chip (PSoC) devices. The PSoC Designer IDE runs
on Windows XP or Windows Vista.
This system provides design database management by project,
an integrated debugger with In-Circuit Emulator, in-system
programming support, and built-in support for third-party
assemblers and C compilers.
Assemblers. The assemblers allow assembly code to merge
seamlessly with C code. Link libraries automatically use absolute
addressing or are compiled in relative mode, and linked with
other software modules to get absolute addressing.
PSoC Designer also supports C language compilers developed
specifically for the devices in the PSoC family.
C Language Compilers. C language compilers are available
that support the PSoC family of devices. The products allow you
to create complete C programs for the PSoC family devices.
5.1 PSoC Designer Software Subsystems
The optimizing C compilers provide all the features of C tailored
to the PSoC architecture. They come complete with embedded
libraries providing port and bus operations, standard keypad and
display support, and extended math functionality.
5.1.1 System-Level View
A drag-and-drop visual embedded system design environment
based on PSoC Express. In the system level view you create a
model of your system inputs, outputs, and communication inter-
faces. You define when and how an output device changes state
based upon any or all other system devices. Based upon the
design, PSoC Designer automatically selects one or more PSoC
Mixed-Signal Controllers that match your system requirements.
5.1.5 Debugger
The PSoC Designer Debugger subsystem provides hardware
in-circuit emulation, allowing you to test the program in a physical
system while providing an internal view of the PSoC device.
Debugger commands allow the designer to read and program
and read and write data memory, read and write I/O registers,
read and write CPU registers, set and clear breakpoints, and
provide program run, halt, and step control. The debugger also
allows the designer to create a trace buffer of registers and
memory locations of interest.
PSoC Designer generates all embedded code, then compiles
and links it into a programming file for a specific PSoC device.
5.1.2 Chip-Level View
The chip-level view is a more traditional integrated development
environment (IDE) based on PSoC Designer 4.4. Choose a base
device to work with and then select different onboard analog and
digital components called user modules that use the PSoC
blocks. Examples of user modules are ADCs, DACs, Amplifiers,
and Filters. Configure the user modules for your chosen
application and connect them to each other and to the proper
pins. Then generate your project. This prepopulates your project
with APIs and libraries that you can use to program your
application.
5.1.6 Online Help System
The online help system displays online, context-sensitive help
for the user. Designed for procedural and quick reference, each
functional subsystem has its own context-sensitive help. This
system also provides tutorials and links to FAQs and an Online
Support Forum to aid the designer in getting started.
5.2 In-Circuit Emulator
The device editor also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic
configuration allows for changing configurations at run time.
A low cost, high functionality ICE (In-Circuit Emulator) is
available for development support. This hardware has the
capability to program single devices.
5.1.3 Hybrid Designs
The emulator consists of a base unit that connects to the PC by
way of a USB port. The base unit is universal and operates with
all PSoC devices. Emulation pods for each device family are
available separately. The emulation pod takes the place of the
PSoC device in the target board and performs full speed (24
MHz) operation.
You can begin in the system-level view, allow it to choose and
configure your user modules, routing, and generate code, then
switch to the chip-level view to gain complete control over
on-chip resources. All views of the project share a common code
editor, builder, and common debug, emulation, and programming
tools.
Document Number: 38-12018 Rev. *M
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CY8C24094, CY8C24794
CY8C24894, CY8C24994
6.3 Organize and Connect
6. Designing with PSoC Designer
You can build signal chains at the chip level by interconnecting
user modules to each other and the I/O pins, or connect system
level inputs, outputs, and communication interfaces to each
other with valuator functions.
The development process for the PSoC device differs from that
of a traditional fixed function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture a
unique flexibility that pays dividends in managing specification
change during development and by lowering inventory costs.
These configurable resources, called PSoC Blocks, have the
ability to implement a wide variety of user-selectable functions.
In the system-level view, selecting a potentiometer driver to
control a variable speed fan driver and setting up the valuators
to control the fan speed based on input from the pot selects,
places, routes, and configures a programmable gain amplifier
(PGA) to buffer the input from the potentiometer, an analog to
digital converter (ADC) to convert the potentiometer’s output to
a digital signal, and a PWM to control the fan.
The PSoC development process can be summarized in the
following four steps:
1. Select components
2. Configure components
3. Organize and Connect
4. Generate, Verify, and Debug
In the chip-level view, perform the selection, configuration, and
routing so that you have complete control over the use of all
on-chip resources.
6.4 Generate, Verify, and Debug
6.1 Select Components
When you are ready to test the hardware configuration or move
on to developing code for the project, perform the “Generate
Application” step. This causes PSoC Designer to generate
source code that automatically configures the device to your
specification and provides the software for the system.
Both the system-level and chip-level views provide a library of
prebuilt, pretested hardware peripheral components. In the
system-level view, these components are called “drivers” and
correspond to inputs (a thermistor, for example), outputs (a
brushless DC fan, for example), communication interfaces
(I C-bus, for example), and the logic to control how they interact
with one another (called valuators).
2
Both system-level and chip-level designs generate software
based on your design. The chip-level design provides application
programming interfaces (APIs) with high level functions to
control and respond to hardware events at run-time and interrupt
service routines that you can adapt as needed. The system-level
design also generates a C main() program that completely
controls the chosen application and contains placeholders for
custom code at strategic positions allowing you to further refine
the software without disrupting the generated code.
In the chip-level view, the components are called “user modules”.
User modules make selecting and implementing peripheral
devices simple, and come in analog, digital, and mixed signal
varieties.
6.2 Configure Components
Each of the components you select establishes the basic register
settings that implement the selected function. They also provide
parameters and properties that allow you to tailor their precise
configuration to your particular application. For example, a Pulse
Width Modulator (PWM) User Module configures one or more
digital PSoC blocks, one for each 8 bits of resolution. The user
module parameters permit you to establish the pulse width and
duty cycle. Configure the parameters and properties to
correspond to your chosen application. Enter values directly or
by selecting values from drop-down menus.
A complete code development environment allows you to
develop and customize your applications in C, assembly
language, or both.
The last step in the development process takes place inside the
PSoC Designer’s Debugger subsystem. The Debugger
downloads the HEX image to the In-Circuit Emulator (ICE) where
it runs at full speed. Debugger capabilities rival those of systems
costing many times more. In addition to traditional single-step,
run-to-breakpoint and watch-variable features, the Debugger
provides a large trace buffer and allows you define complex
breakpoint events that include monitoring address and data bus
values, memory locations and external signals.
Both the system-level drivers and chip-level user modules are
documented in data sheets that are viewed directly in the PSoC
Designer. These data sheets explain the internal operation of the
component and provide performance specifications. Each data
sheet describes the use of each user module parameter or driver
property, and other information you may need to successfully
implement your design.
Document Number: 38-12018 Rev. *M
Page 6 of 47
CY8C24094, CY8C24794
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7.2 Units of Measure
7. Document Conventions
A units of measure table is located in the Electrical Specifications
measure the PSoC devices.
7.1 Acronyms Used
The following table lists the acronyms that are used in this
document.
7.3 Numeric Naming
Acronym
AC
Description
alternating current
Hexadecimal numbers are represented with all letters in
uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or
‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’
prefix, the C coding convention. Binary numbers have an
appended lowercase ‘b’ (e.g., 01010100b’ or ‘01000011b’).
Numbers not indicated by an ‘h’ or ‘b’ are decimal.
ADC
API
analog-to-digital converter
application programming interface
central processing unit
continuous time
CPU
CT
DAC
DC
digital-to-analog converter
direct current
ECO
external crystal oscillator
EEPROM electrically erasable programmable read-only
memory
FSR
GPI/O
GUI
full scale range
general purpose I/O
graphical user interface
human body model
in-circuit emulator
HBM
ICE
ILO
internal low speed oscillator
internal main oscillator
input/output
IMO
I/O
IPOR
LSb
imprecise power on reset
least-significant bit
LVD
low voltage detect
MSb
PC
most-significant bit
program counter
PLL
phase-locked loop
POR
PPOR
PSoC®
PWM
SC
power on reset
precision power on reset
Programmable System-on-Chip™
pulse width modulator
switched capacitor
SRAM
static random access memory
Document Number: 38-12018 Rev. *M
Page 7 of 47
CY8C24094, CY8C24794
CY8C24894, CY8C24994
8. Pin Information
This section describes, lists, and illustrates the CY8C24x94 PSoC device family pins and pinout configuration.
The CY8C24x94 PSoC devices are available in the following packages, all of which are shown on the following pages. Every port pin
(labeled with a “P”) is capable of Digital I/O. However, Vss, Vdd, and XRES are not capable of Digital I/O.
8.1 56-Pin Part Pinout
Type
Digital Analog
Pin
No.
Figure 8-1. CY8C24794 56-Pin PSoC Device
Name
Description
1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I, M
I, M
M
P2[3] Direct switched capacitor block input.
2
3
4
P2[1] Direct switched capacitor block input.
P4[7]
P4[5]
M
5
6
7
M
M
M
P4[3]
P4[1]
P3[7]
A,I, M,P2[3]
A,I, M,P2[1]
M,P4[7]
1
2
P2[2], A, I,M
P2[0], A, I,M
P4[6],M
P4[4],M
P4[2],M
P4[0],M
P3[6],M
P3[4],M
P3[2],M
P3[0],M
P5[6],M
P5[4],M
P5[2],M
P5[0],M
42
41
3
4
5
6
40
39
8
9
M
M
M
P3[5]
P3[3]
P3[1]
M,P4[5]
M,P4[3]
M,P4[1]
38
37
36
35
34
33
32
31
30
29
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
M,P3[7]
7
8
9
10
11
12
13
14
M
M
M
P5[7]
P5[5]
P5[3]
QFN
(Top View )
M,P3[5]
M,P3[3]
M,P3[1]
M
M
M
P5[1]
M,P5[7]
M,P5[5]
M,P5[3]
M,P5[1]
P1[7] I2C Serial Clock (SCL).
P1[5] I2C Serial Data (SDA).
P1[3]
M
M
P1[1] I2C Serial Clock (SCL), ISSP SCLK
.
Power
Vss Ground connection.
USB
USB
D+
D-
Power
Vdd Supply voltage.
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P7[7]
P7[0]
M
M
M
M
M
P1[0] I2C Serial Data (SDA), ISSP SDATA
P1[2]
.
P1[4] Optional External Clock Input (EXTCLK).
P1[6]
P5[0]
Type
Pin
No.
Name
Description
30
31
32
33
34
35
36
37
38
39
40
41
42
43
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
M
M
M
M
M
M
M
M
M
M
M
P5[2]
Digital Analog
P5[4]
44
45
46
47
48
49
50
51
52
53
54
55
56
I/O
I/O
I/O
I/O
I/O
M
P2[6] External Voltage Reference (VREF) input.
P0[0] Analog column mux input.
P0[2] Analog column mux input.
P0[4] Analog column mux input VREF.
P0[6] Analog column mux input.
Vdd Supply voltage.
P5[6]
I, M
I, M
I, M
I, M
P3[0]
P3[2]
P3[4]
P3[6]
Power
Power
I, M
P4[0]
Vss Ground connectI/On.
P4[2]
I/O
I/O
I/O
I/O
I/O
I/O
P0[7] Analog column mux input,.
P4[4]
I/O, M P0[5] Analog column mux input and column output.
I/O, M P0[3] Analog column mux input and column output.
P4[6]
I, M
I, M
M
P2[0] Direct switched capacitor block input.
P2[2] Direct switched capacitor block input.
P2[4] External Analog Ground (AGND) input.
I, M
M
P0[1] Analog column mux input.
P2[7]
P2[5]
M
Document Number: 38-12018 Rev. *M
Page 8 of 47
CY8C24094, CY8C24794
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8.1 56-Pin Part Pinout (with XRES)
Type
Pin
Figure 8-2. CY8C24894 56-Pin PSoC Device
Name
Description
No.
Digital Analog
1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I, M
I, M
M
P2[3] Direct switched capacitor block input.
2
3
4
P2[1] Direct switched capacitor block input.
P4[7]
P4[5]
M
5
6
7
M
M
M
P4[3]
P4[1]
P3[7]
A, I, M, P2[3]
A, I, M, P2[1]
1
2
P2[2], A, I, M
P2[0], A, I, M
42
41
40
39
38
37
8
9
M
M
M
P3[5]
P3[3]
P3[1]
M, P4[7]
M, P4[5]
M, P4[3]
M, P4[1]
M, P3[7]
3
4
5
6
P4[6], M
P4[4], M
P4[2], M
P4[0], M
XRES
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
M
M
M
P5[7]
P5[5]
P5[3]
7
8
QFN
(Top View)
36
35
34
33
M, P3[5]
M, P3[3]
M, P3[1]
P3[4], M
P3[2], M
P3[0], M
9
M
M
M
P5[1]
10
P1[7] I2C Serial Clock (SCL).
P1[5] I2C Serial Data (SDA).
P1[3]
M, P5[7]
M, P5[5]
M, P5[3]
M, P5[1]
11
12
13
14
P5[6], M
P5[4], M
P5[2], M
P5[0], M
32
31
30
29
M
M
P1[1] I2C Serial Clock (SCL), ISSP SCLK
Power
Vss Ground connection.
USB
USB
D+
D-
Power
Vdd Supply voltage.
I/O
I/O
I/O
I/O
I/O
I/O
P7[7]
P7[0]
M
M
M
M
P1[0] I2C Serial Data (SDA), ISSP SDATA
P1[2]
.
P1[4] Optional External Clock Input (EXTCLK).
P1[6]
29
30
31
32
33
34
35
36
I/O
I/O
I/O
I/O
I/O
I/O
I/O
M
M
M
M
M
M
M
P5[0]
P5[2]
P5[4]
P5[6]
P3[0]
P3[2]
P3[4]
Type
Pin
No.
Name
Description
Digital Analog
44
45
46
47
48
49
I/O
I/O
I/O
I/O
I/O
M
P2[6] External Voltage Reference (VREF) input.
P0[0] Analog column mux input.
P0[2] Analog column mux input.
P0[4] Analog column mux input VREF.
P0[6] Analog column mux input.
Vdd Supply voltage.
I, M
I, M
I, M
I, M
Input
XRES Active high external reset with internal
pull down.
Power
37
38
39
40
41
42
43
I/O
I/O
I/O
I/O
I/O
I/O
I/O
M
M
M
M
P4[0]
50
51
52
53
54
55
56
Power
I, M
Vss Ground connection.
P4[2]
I/O
I/O
I/O
I/O
I/O
I/O
P0[7] Analog column mux input,.
P4[4]
I/O, M P0[5] Analog column mux input and column output.
I/O, M P0[3] Analog column mux input and column output.
P4[6]
I, M
I, M
M
P2[0] Direct switched capacitor block input.
P2[2] Direct switched capacitor block input.
P2[4] External Analog Ground (AGND) input.
I, M
M
P0[1] Analog column mux input.
P2[7]
P2[5]
M
LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input.
Notes
1. These are the ISSP pins, which are not High Z at POR. See the PSoC Programmable System-on-Chip Technical Reference Manual for details.
2. The center pad on the QFN package should be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to ground, it
should be electrically floated and not connected to any other signal.
Document Number: 38-12018 Rev. *M
Page 9 of 47
CY8C24094, CY8C24794
CY8C24894, CY8C24994
8.1 68-Pin Part Pinout
The 68-pin QFN part table and drawing below is for the CY8C24994 PSoC device.
Type
Figure 8-3. CY8C24994 68-Pin PSoC Device
Pin
No.
Name
Description
Digital Analog
1
I/O
I/O
I/O
I/O
M
M
M
M
P4[7]
P4[5]
P4[3]
P4[1]
NC
2
3
4
5
6
7
8
9
No connection.
No connection.
NC
Power
I/O
Vss
Ground connection.
M, P4[7]
M, P4[5]
M, P4[3]
P2[0], M, AI
51
1
2
M
M
M
M
M
M
M
M
M
M
M
M
P3[7]
P3[5]
P3[3]
P3[1]
P5[7]
P5[5]
P5[3]
P5[1]
P1[7]
P1[5]
P1[3]
P1[1]
Vss
50
P4[6], M
P4[4], M
P4[2], M
I/O
3
4
49
48
47
46
M, P4[1]
NC
10 I/O
11 I/O
5
6
P4[0], M
XRES
NC
NC
12 I/O
13 I/O
14 I/O
15 I/O
16 I/O
17 I/O
18 I/O
19 I/O
20 Power
21 USB
22 USB
23 Power
24 I/O
25 I/O
26 I/O
27 I/O
28 I/O
29 I/O
30 I/O
31 I/O
32 I/O
33 I/O
34 I/O
35 I/O
36 I/O
37 I/O
38 I/O
39 I/O
40 I/O
41 I/O
42 I/O
43 I/O
Vss
M, P3[7]
M, P3[5]
45
7
8
9
NC
P3[6], M
P3[4], M
44
43
42
QFN
(Top View)
10
M, P3[3]
M, P3[1]
M, P5[7]
P3[2], M
P3[0], M
11
12
13
14
15
41
I2C Serial Clock (SCL).
I2C Serial Data (SDA).
40
39
M, P5[5]
P5[6], M
P5[4], M
M, P5[3]
M, P5[1]
I2C SCL, M, P1[7]
I2C SDA, M, P1[5]
38
37
36
35
P5[2], M
P5[0], M
[1]
I2C Serial Clock (SCL) ISSP SCLK
Ground connection.
.
16
17
P1[6], M
D+
D-
Vdd
Supply voltage.
P7[7]
P7[6]
P7[5]
P7[4]
P7[3]
P7[2]
P7[1]
P7[0]
P1[0]
P1[2]
P1[4]
P1[6]
P5[0]
P5[2]
P5[4]
P5[6]
P3[0]
P3[2]
P3[4]
P3[6]
Type
Pin
No.
Name
Description
Digital Analog
50 I/O
51 I/O
52 I/O
M
P4[6]
M
M
M
M
M
M
M
M
M
M
M
M
I2C Serial Data (SDA), ISSP SDATA
.
I,M
I,M
M
P2[0] Direct switched capacitor block input.
P2[2] Direct switched capacitor block input.
P2[4] External Analog Ground (AGND) input.
P2[6] External Voltage Reference (VREF) input.
P0[0] Analog column mux input.
Optional External Clock Input (EXTCLK). 53 I/O
54 I/O
55 I/O
56 I/O
57 I/O
58 I/O
M
I,M
I,M
I,M
I,M
P0[2] Analog column mux input and column output.
P0[4] Analog column mux input and column output.
P0[6] Analog column mux input.
59 Power
Vdd
Vss
Supply voltage.
60 Power
61 I/O
Ground connection.
I,M
P0[7] Analog column mux input, integration input #1
62 I/O
I/O,M
P0[5] Analog column mux input and column output, integration
input #2.
44
NC
NC
No connection.
No connection.
63 I/O
64 I/O
65 I/O
I/O,M
I,M
P0[3] Analog column mux input and column output.
P0[1] Analog column mux input.
P2[7]
45
46 Input
XRES Active high pin reset with internal pull
down.
M
47 I/O
48 I/O
49 I/O
M
M
M
P4[0]
P4[2]
P4[4]
66 I/O
67 I/O
68 I/O
M
P2[5]
I,M
I,M
P2[3] Direct switched capacitor block input.
P2[1] Direct switched capacitor block input.
LEGENDA = Analog, I = Input, O = Output, NC = No Connection, M = Analog Mux Input.
Document Number: 38-12018 Rev. *M
Page 10 of 47
CY8C24094, CY8C24794
CY8C24894, CY8C24994
8.1 68-Pin Part Pinout (On-Chip Debug)
The 68-pin QFN part table and drawing below is for the CY8C24094 On-Chip Debug (OCD) PSoC device.
Note This part is only used for in-circuit debugging. It is NOT available for production.
Type
Pin
No.
Figure 8-4. CY8C24094 68-Pin OCD PSoC Device
Name
Description
Digital Analog
1
I/O
I/O
I/O
I/O
M
M
M
M
P4[7]
P4[5]
P4[3]
P4[1]
2
3
4
5
6
7
8
9
OCDE OCD even data I/O.
OCDO OCD odd data output.
Power
I/O |