Cypress Computer Hardware CY7C1019D User Manual

CY7C1019D  
1-Mbit (128K x 8) Static RAM  
Features  
Functional Description [1]  
• Pin- and function-compatible with CY7C1019B  
• High speed  
The CY7C1019D is a high-performance CMOS static RAM  
organized as 131,072 words by 8 bits. Easy memory  
expansion is provided by an active LOW Chip Enable (CE), an  
active LOW Output Enable (OE), and tri-state drivers. This  
device has an automatic power-down feature that significantly  
reduces power consumption when deselected. The eight input  
— t = 10 ns  
AA  
• Low active power  
— I = 80 mA @ 10 ns  
CC  
and output pins (IO through IO ) are placed in  
high-impedance state when:  
a
0
7
• Low CMOS standby power  
— I  
= 3 mA  
SB2  
• Deselected (CE HIGH)  
• 2.0V Data retention  
• Outputs are disabled (OE HIGH)  
• Automatic power-down when deselected  
• CMOS for optimum speed/power  
• Center power/ground pinout  
• When the write operation is active (CE LOW, and WELOW).  
Write to the device by taking Chip Enable (CE) and Write  
Enable (WE) inputs LOW. Data on the eight IO pins (IO  
0
through IO ) is then written into the location specified on the  
7
• Easy memory expansion with CE and OE options  
• Functionally equivalent to CY7C1019B  
address pins (A through A ).  
0
16  
Read from the device by taking Chip Enable (CE) and Output  
Enable (OE) LOW while forcing Write Enable (WE) HIGH.  
Under these conditions, the contents of the memory location  
specified by the address pins appears on the IO pins.  
• Available in Pb-free 32-pin 400-Mil wide Molded SOJ and  
32-pin TSOP II packages  
Logic Block Diagram  
IO  
0
INPUT BUFFER  
IO  
1
A
0
IO  
2
A
1
A
2
128K x 8  
IO  
3
A
3
A
4
ARRAY  
IO  
4
A
5
A
6
IO  
5
A
7
A
8
IO  
6
CE  
IO  
POWER  
DOWN  
7
COLUMN DECODER  
WE  
OE  
Note  
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05464 Rev. *E  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised February 22, 2007  
 
CY7C1019D  
Current into Outputs (LOW) ........................................ 20 mA  
Maximum Ratings  
Static Discharge Voltage........................................... > 2001V  
(per MIL-STD-883, Method 3015)  
Exceeding the maximum ratings may impair the useful life of  
the device. These user guidelines are not tested.  
Latch-up Current .................................................... > 200 mA  
Storage Temperature .................................65°C to +150°C  
Ambient Temperature with  
Operating Range  
Power Applied.............................................55°C to +125°C  
[2]  
Ambient  
Temperature  
Supply Voltage on V to Relative GND ... –0.5V to +6.0V  
CC  
Range  
V
Speed  
CC  
DC Voltage Applied to Outputs  
[2]  
Industrial  
–40°C to +85°C  
5V ± 0.5V  
10 ns  
in High-Z State ...................................–0.5V to V + 0.5V  
CC  
[2]  
DC Input Voltage ................................–0.5V to V + 0.5V  
CC  
Electrical Characteristics (Over the Operating Range)  
–10 (Industrial)  
Parameter  
Description  
Test Conditions  
Unit  
Min  
Max  
V
Output HIGH Voltage  
I
I
= –4.0 mA  
2.4  
V
V
OH  
OL  
IH  
OH  
V
V
V
I
Output LOW Voltage  
Input HIGH Voltage  
= 8.0 mA  
0.4  
OL  
2.2  
–0.5  
–1  
V
+ 0.5  
V
CC  
[2]  
Input LOW Voltage  
0.8  
+1  
+1  
80  
72  
58  
37  
10  
V
IL  
Input Leakage Current  
Output Leakage Current  
GND < V < V  
CC  
µA  
µA  
mA  
mA  
mA  
mA  
mA  
IX  
I
I
I
GND < V < V , Output Disabled  
–1  
OZ  
I
CC  
V
Operating Supply Current  
V
= Max,  
100 MHz  
83 MHz  
66 MHz  
40 MHz  
CC  
CC  
CC  
I
= 0 mA,  
OUT  
f = f  
= 1/t  
max  
RC  
I
I
Automatic CE Power-Down  
Current—TTL Inputs  
Max V , CE > V  
CC IH  
V
SB1  
SB2  
> V or V < V , f = f  
IN  
IH IN IL max  
Automatic CE Power-Down  
Current—CMOS Inputs  
Max V , CE > V – 0.3V,  
V
3
mA  
CC  
CC  
> V – 0.3V, or V < 0.3V, f = 0  
IN  
CC  
IN  
Note  
2.  
V
(min) = –2.0V and V (max) = V + 1V for pulse durations of less than 5 ns.  
IH CC  
IL  
Document #: 38-05464 Rev. *E  
Page 3 of 11  
 
CY7C1019D  
Capacitance [3]  
Parameter  
Description  
Input Capacitance  
Output Capacitance  
Test Conditions  
Max  
6
Unit  
pF  
C
C
T = 25°C, f = 1 MHz, V = 5.0V  
CC  
IN  
A
8
pF  
OUT  
Thermal Resistance [3]  
400-Mil  
Wide SOJ  
Parameter  
Description  
Test Conditions  
TSOP II  
Unit  
Θ
Thermal Resistance  
(Junction to Ambient)  
Still Air, soldered on a 3 × 4.5 inch,  
four-layer printed circuit board  
56.29  
62.22  
°C/W  
JA  
Θ
Thermal Resistance  
(Junction to Case)  
38.14  
21.43  
°C/W  
JC  
AC Test Loads and Waveforms [4]  
ALL INPUT PULSES  
3.0V  
Z = 50Ω  
90%  
10%  
90%  
10%  
OUTPUT  
50Ω  
GND  
30 pF*  
* CAPACITIVE LOAD CONSISTS  
OF ALL COMPONENTS OF THE  
TEST ENVIRONMENT  
1.5V  
Fall Time: 3 ns  
Rise Time: 3 ns  
(b)  
(a)  
High-Z characteristics:  
R1 480Ω  
5V  
OUTPUT  
R2  
255Ω  
5 pF  
INCLUDING  
JIG AND  
SCOPE  
(c)  
Notes  
3. Tested initially and after any design or process changes that may affect these parameters.  
4. AC characteristics (except High-Z) are tested using the load conditions shown in Figure (a). High-Z characteristics are tested for all speeds using the test load  
shown in Figure (c).  
Document #: 38-05464 Rev. *E  
Page 4 of 11  
 
CY7C1019D  
[5]  
Switching Characteristics (Over the Operating Range)  
–10 (Industrial)  
Min Max  
Parameter  
Description  
Unit  
Read Cycle  
[6]  
t
V
(typical) to the first access  
100  
10  
µs  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
power  
CC  
t
t
t
t
t
t
t
t
t
t
t
Read Cycle Time  
RC  
Address to Data Valid  
10  
AA  
Data Hold from Address Change  
CE LOW to Data Valid  
OE LOW to Data Valid  
OE LOW to Low Z  
3
OHA  
ACE  
DOE  
LZOE  
HZOE  
LZCE  
HZCE  
10  
5
0
3
0
[7, 8]  
OE HIGH to High Z  
5
5
[8]  
CE LOW to Low Z  
[7, 8]  
CE HIGH to High Z  
[9]  
CE LOW to Power-Up  
PU  
[9]  
CE HIGH to Power-Down  
10  
PD  
[10, 11]  
Write Cycle  
t
t
t
t
t
t
t
t
t
t
Write Cycle Time  
10  
7
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
WC  
CE LOW to Write End  
SCE  
AW  
Address Set-Up to Write End  
Address Hold from Write End  
Address Set-Up to Write Start  
WE Pulse Width  
7
0
HA  
0
SA  
7
PWE  
SD  
Data Set-Up to Write End  
Data Hold from Write End  
6
0
HD  
[8]  
WE HIGH to Low Z  
3
LZWE  
HZWE  
[7, 8]  
WE LOW to High Z  
5
Notes  
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified  
I
t
t
/I and 30-pF load capacitance.  
OL OH  
6.  
7.  
gives the minimum amount of time that the power supply should be at typical V values until the first memory access can be performed.  
CC  
POWER  
[4]  
, t  
, and t  
are specified with a load capacitance of 5 pF as in (c) of “AC Test Loads and Waveforms ” on page 4. Transition is measured when the outputs enter a  
HZOE HZCE  
HZWE  
high impedance state.  
8. At any given temperature and voltage condition, t  
is less than t  
, t  
is less than t  
, and t  
is less than t  
for any given device.  
HZCE  
LZCE HZOE  
LZOE  
HZWE  
LZWE  
9. This parameter is guaranteed by design and is not tested.  
10. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of  
these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.  
11. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of t  
and t  
.
HZWE  
SD  
Document #: 38-05464 Rev. *E  
Page 5 of 11  
 
CY7C1019D  
Data Retention Characteristics (Over the Operating Range)  
Parameter  
Description  
Conditions  
Min  
Max  
Unit  
V
V
V
for Data Retention  
2.0  
DR  
CC  
I
Data Retention Current  
V
V
= V = 2.0V, CE > V – 0.3V,  
3
mA  
CCDR  
CC  
DR  
CC  
> V – 0.3V or V < 0.3V  
IN  
CC  
IN  
[3]  
t
t
Chip Deselect to Data Retention Time  
Operation Recovery Time  
0
ns  
ns  
CDR  
[12]  
t
R
RC  
Data Retention Waveform  
DATA RETENTION MODE  
DR > 2V  
4.5V  
4.5V  
V
V
CC  
t
t
R
CDR  
CE  
Switching Waveforms  
[13, 14]  
Read Cycle No. 1 (Address Transition Controlled)  
tRC  
ADDRESS  
t
AA  
t
OHA  
DATA OUT  
PREVIOUS DATA VALID  
DATA VALID  
[14, 15]  
Read Cycle No. 2 (OE Controlled)  
ADDRESS  
CE  
t
RC  
t
ACE  
OE  
t
HZOE  
t
DOE  
t
HZCE  
t
LZOE  
HIGH  
IMPEDANCE  
HIGH IMPEDANCE  
DATA OUT  
DATA VALID  
t
LZCE  
t
PD  
V
CC  
ICC  
t
PU  
SUPPLY  
CURRENT  
50%  
50%  
ISB  
Notes  
12. Full device operation requires linear V ramp from V to V  
> 50 µs or stable at V > 50 µs.  
CC(min)  
CC  
DR  
CC(min)  
13. Device is continuously selected. OE, CE = V .  
IL  
14. WE is HIGH for Read cycle.  
15. Address valid prior to or coincident with CE transition LOW.  
Document #: 38-05464 Rev. *E  
Page 6 of 11  
 
CY7C1019D  
Switching Waveforms (continued)  
[16, 17]  
Write Cycle No. 1 (CE Controlled)  
t
WC  
ADDRESS  
CE  
t
SCE  
t
SA  
t
SCE  
t
t
HA  
AW  
t
PWE  
WE  
t
t
HD  
SD  
DATA IO  
DATA VALID  
[16, 17]  
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)  
t
WC  
ADDRESS  
t
SCE  
CE  
t
t
HA  
AW  
t
t
PWE  
SA  
WE  
OE  
t
t
SD  
HD  
DATA VALID  
DATA IO  
IN  
NOTE 18  
t
HZOE  
Notes  
16. Data IO is high impedance if OE = V  
.
IH  
17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.  
18. During this period the IOs are in the output state and input signals should not be applied.  
Document #: 38-05464 Rev. *E  
Page 7 of 11  
 
CY7C1019D  
Switching Waveforms (continued)  
[11, 17]  
Write Cycle No. 3 (WE Controlled, OE LOW)  
t
WC  
ADDRESS  
CE  
t
SCE  
t
t
HA  
AW  
t
SA  
t
PWE  
WE  
t
t
HD  
SD  
DATA IO  
NOTE 18  
DATA VALID  
t
t
LZWE  
HZWE  
Truth Table  
CE  
H
L
OE  
WE  
X
IO –IO  
Mode  
Power  
0
7
X
L
High Z  
Power-Down  
Read  
Standby (I  
)
SB  
H
Data Out  
Data In  
High Z  
Active (I  
Active (I  
Active (I  
)
CC  
L
X
H
L
Write  
)
CC  
L
H
Selected, Outputs Disabled  
)
CC  
Ordering Information  
Speed  
Package  
Diagram  
Operating  
Range  
Ordering Code  
CY7C1019D-10VXI  
CY7C1019D-10ZSXI  
Package Type  
(ns)  
10  
51-85033 32-pin (400-Mil) Molded SOJ (Pb-free)  
51-85095 32-pin TSOP Type II (Pb-free)  
Industrial  
Please contact your local Cypress sales representative for availability of these parts.  
Document #: 38-05464 Rev. *E  
Page 8 of 11  
 
CY7C1019D  
Package Diagrams  
Figure 1. 32-pin (400-Mil) Molded SOJ (51-85033)  
51-85033-*B  
Document #: 38-05464 Rev. *E  
Page 9 of 11  
 
CY7C1019D  
Package Diagrams (continued)  
Figure 2. 32-pin Thin Small Outline Package Type II (51-85095)  
51-85095-**  
All product or company names mentioned in this document may be the trademarks of their respective holders.  
Document #: 38-05464 Rev. *E  
Page 10 of 11  
© Cypress Semiconductor Corporation, 2006-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for  
the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended  
to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize  
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
 
CY7C1019D  
Document History Page  
Document Title: CY7C1019D, 1-Mbit (128K x 8) Static RAM  
Document Number: 38-05464  
Orig. of  
Change  
REV.  
ECN NO.  
Issue Date  
Description of Change  
**  
201560  
233715  
See ECN  
See ECN  
SWI  
Advance Information data sheet for C9 IPP  
*A  
RKF  
DC parameters are modified as per EROS (Spec # 01-2165)  
Pb-free offering in the Ordering Information  
*B  
262950  
See ECN  
RKF  
Added T  
Spec in Switching Characteristics table  
power  
Added Data Retention Characteristics table and waveforms  
Shaded Ordering Information  
*C  
*D  
307598  
520647  
See ECN  
See ECN  
RKF  
VKN  
Reduced Speed bins to -10 and -12 ns  
Converted from Preliminary to Final  
Removed Commercial Operating range  
Removed 12 ns speed bin  
Added I values for the frequencies 83MHz, 66MHz and 40MHz  
CC  
Updated Thermal Resistance table  
Updated Ordering Information Table  
Changed Overshoot spec from V +2V to V +1V in footnote #2  
CC  
CC  
*E  
802877  
See ECN  
VKN  
Changed I spec from 60 mA to 80 mA for 100MHz, 55 mA to 72 mA  
for 83MHz, 45 mA to 58 mA for 66MHz, 30 mA to 37 mA for 40MHz  
CC  
Document #: 38-05464 Rev. *E  
Page 11 of 11  
 

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